1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a plurality of memory blocks arranged in a matrix of rows and columns and enabling simultaneous input/output of a plurality of pieces of data.
2. Description of the Background Art
FIG. 15 is a block diagram showing a configuration of a conventional dynamic random access memory (hereinafter referred to as DRAM) used as a memory to be mounted together with a logic circuit. In FIG. 15, the DRAM includes sixteen memory blocks MB arranged in four rows and four columns. The sixteen memory blocks MB are separated and enclosed by five sense amplifier zones 71 and five sub decoder zones 72.
A main row decoder MRD is provided at one end of each row of memory blocks MB. A number of sub row decoders (not shown) are dispersedly arranged at each sub decoder zone 72. Each sense amplifier zone 71 is provided with eight column selecting lines CSL0 to CSL7 and also with a number of sense amplifiers (not shown) that are dispersedly arranged. One end of each of the eight column selecting lines CSL0 to CSL7 is connected to a column decoder CD. A data input/output line pair group 73 is provided corresponding to each column of memory blocks MB. One end of each data input/output line pair group 73 is connected to a write/read circuit 74.
Four main row decoders MRD and sub decoders select, for example, one memory block MB row and one word line of each memory block MB in the selected row, and activate a plurality of memory cells corresponding to the selected word line. Further, one column selecting line is selected from sixteen column selecting lines CSL0 to CSL7 and CSL0 to CSL 7 arranged at either side of the selected memory block MB row by column decoders CD, and a plurality of memory cells corresponding to the selected column selecting line among the activated plurality of memory cells in each memory block MB are connected to write/read circuit 74 via data input/output line pair group 73. Write/read circuit 74 performs writing/reading of data in each of the activated memory cells via each data input/output line pair group 73. The DRAM enables simultaneous input/output of multiple pieces of data.
However, such a DRAM has a problem in that longer line-routing and larger capacitance value of column selecting lines CSL0 to CSL7 would deaden a waveform of an output signal of column decoder CD, making faster column selecting operation difficult.
FIG. 16 is a block diagram showing a configuration of another conventional DRAM. The DRAM in FIG. 16 is different from the DRAM in FIG. 15 in that eight sub column selecting lines SCSL0 to SCSL7 and a repeater RP are added corresponding to each memory block MB in each sense amplifier zone 71. Repeater RP changes the level of sub column selecting lines SCSL0 to SCSL7 in response to that the level of sub column selecting lines SCSL0 to SCSL7 has exceeded a predetermined threshold potential. A plurality of memory cells, corresponding to the sub column selecting lines that are set to be at a selected level, of a plurality of activated memory cells in each memory block MB are connected to write/read circuit 74 via a data input/output line pair group (not shown). In this DRAM, a waveform of an output signal of column decoder CD can be regenerated by repeater RP, so that faster column selecting operation is enabled.
However, the DRAM in FIG. 16 has a problem in that eight sub column selecting lines SCSL0 to SCSL7 must be arranged in parallel with eight column selecting lines CSL0 to CSL7 in each sense amplifier zone 71, increasing the area of sense amplifier zone 71.
Therefore, a main object of the present invention is to provide a semiconductor memory device having a small area of a first zonal region and a fast operation speed.
In a semiconductor memory device according to the present invention, a column selecting circuit includes a plurality of first signal transmission lines provided corresponding to each memory block row and arranged to extend along the length of a first zonal region adjacent to a corresponding memory block row; a plurality of second signal transmission lines provided corresponding to each memory block column and arranged to extend along the length of a second zonal region adjacent to a corresponding memory block column; a first decoder provided corresponding to each memory block row and generating a first predecode signal based on a column address signal to apply the first predecode signal to a plurality of corresponding first signal transmission lines; a second decoder provided corresponding to each memory block column and generating a second predecode signal based on the column address signal to apply the second predecode signal to a plurality of corresponding second signal transmission lines; and a third decoder provided corresponding to each memory block and arranged at a crossing portion of the first and second zonal regions adjacent to a corresponding memory block, and selecting one bit line pair from a plurality of bit line pairs of the corresponding memory block based on the first predecode signal from the plurality of corresponding first signal transmission lines and the second predecode signal from the plurality of corresponding second signal transmission lines. Therefore, the area of the first zonal region may be smaller compared to that of a conventional memory device in which a plurality of signal transmission lines for column selection were provided only in the first zonal region. Further, the third decoder provided at the crossing portion of the first and second zonal regions selects a bit line pair of a memory block in the vicinity of the third decoder, so that the speed of the column selecting operation can be increased.
Preferably, the first predecode signal includes a plurality of first signals respectively applied to the plurality of first signal transmission lines, and the second predecode signal includes a plurality of second signals respectively applied to the plurality of second signal transmission lines. One first signal of the plurality of first signals is set to be at an activated level by the first decoder and one signal of the plurality of second signals is set to be at the activated level. This can make the number of the signal transmission lines smaller.
More preferably, the third decoder includes a plurality of logic circuits respectively provided corresponding to the plurality of column selecting lines and arranged at a plurality of crossing portions of the plurality of first signal transmission lines and the plurality of second signal transmission lines, each of the plurality of logic circuits setting a corresponding column selecting line to be at a selected level in response to that a first signal from a corresponding first signal transmission line and a second signal from a corresponding second signal transmission line are both set to be at the activated level. When the column selecting line is set to be at a selected level, a column selection gate between a bit line pair and a write/read circuit corresponding to the column selecting line is made conductive. This facilitates configuration of the third decoder.
More preferably, the plurality of first signal transmission lines are paired up to constitute a plurality of first signal transmission line pairs; the plurality of second signal transmission lines are paired up to constitute a plurality of second signal transmission line pairs; the first predecode signal includes a plurality of sets of first signals and complementary signals of the first signals respectively applied to the plurality of first signal transmission lines; and the second predecode signal includes a plurality of sets of second signals and complementary signals of the second signals respectively applied to the plurality of second signal transmission lines. One set of a first signal and its complementary signal of the plurality of sets of first signals and their complementary signals are respectively set to be at the first and second selected levels by the first decoder, whereas one set of a second signal and its complementary signal of the plurality sets of the second signals and their complementary signals are respectively set to be at the first and second logic levels by the second decoder. This can reduce the adverse effects of noise.
More preferably, the third decoder includes a plurality of logic circuits respectively provided corresponding to the plurality of column selecting lines and arranged at a plurality of crossing portions of the plurality of first signal transmission line pairs and the plurality of second signal transmission line pairs, each of the plurality of logic circuits setting a corresponding column selecting line to be at a selected level in response to that a first signal and a complementary signal of the first signal from a corresponding first signal transmission line pair are set to be at a first logic level and a second logic level respectively and that a second signal and a complementary signal of the second signal from a corresponding second signal transmission line pair are set to be at the first logic level and the second logic level respectively. When the column selecting line is set to be at the selected level, a column selection gate between a bit line pair and a write/read circuit that are corresponding to the column selecting line is made conductive. This facilitates the configuration of the third decoder.
More preferably, the plurality of second signal transmission lines are separately arranged at second zonal regions on either side of a corresponding memory block column; a plurality of second signal transmission lines arranged at one of the second zonal regions are provided in common to memory block columns at either side of the second zonal region; the third decoder is divided and arranged at a plurality of crossing portions of first zonal regions and second zonal regions adjacent to a corresponding memory block; and a portion of the third decoder arranged at one crossing portion is shared by memory block columns on either side of a second zonal region including the crossing portion. This can make the number of the second signal transmission lines smaller.
More preferably, the plurality of second signal transmission lines are arranged at a second zonal region at one side of a corresponding memory block column. This allows each memory block to select a bit line pair independently from the other memory blocks.
More preferably, the second decoder is inactivated in response to that a write mask signal for inhibiting writing of data into each memory cell in a corresponding memory block column is applied. This can realize a write mask operation.
More preferably, the column selecting circuit includes a word line driving circuit provided corresponding to each word line of each memory block and arranged at a second zonal region adjacent to a corresponding memory block, and setting a corresponding word line to be at a selected level, in response to that the corresponding word line is selected, and the second decoder further inactivates each corresponding word line driving circuit in response to that the write mask signal is applied. This can lower consumption electric power.
More preferably, a plurality of word lines in each memory block are divided into a plurality of groups respectively including N (N is an integer equal to or greater than 2) word lines; the column selecting circuit further includes a fourth decoder provided corresponding to each of the memory block rows to select one group from a plurality of groups of each corresponding memory block in accordance with the row address signal, and a fifth decoder provided corresponding to each memory block to select one word line from N word lines in each corresponding group in accordance with the row address signal; the word line driving circuit is activated in response to that a corresponding group is selected by the forth decoder, and sets a corresponding word line to be at a selected level in response to that the corresponding word line is selected by the fifth decoder; and the second decoder inactivates each corresponding fifth decoder in response to that the write mask signal is applied. This can realize a configuration of divided world lines, so that a column selecting operation can be made faster.
More preferably, the row selecting circuit further includes a plurality of main word lines provided corresponding to each memory block row and arranged to cross a plurality of corresponding memory blocks, and respectively provided corresponding to a plurality of groups of each corresponding memory block, and N third signal transmission lines provided corresponding to each memory block and arranged at a second zonal region adjacent to a corresponding memory block, and respectively provided corresponding to N word lines of each corresponding group. The fourth decoder sets a main word line corresponding to a selected group to be at an activated level, and the fifth decoder sets a third signal transmission line corresponding to a selected word line to be at a selected level. The word line driving circuit is activated in response to that a corresponding main word line is set to be at the activated level, and sets a corresponding word line to be at a selected level in response to that a corresponding third signal transmission line is set to be at the selected level. This facilitates arrangement of the main word lines and the third signal transmission lines for column selection.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.